A. Field of the Invention
This invention relates generally to data communications interfaces and, more particularly, relates to ways for reinitializing the data flow across an interface that is galvanically isolated.
B. Description of Related Art and Problem Solved by the Invention
Data communication interfaces, such as data buses or networks, allow machines such as computer systems, disc drives, printers, and other equipment to exchange information. The machines connected to an interface typically communicate according to a common standard, which invariably defines requirements of the interface control and driver hardware. A common hardware constraint is to require galvanic isolation of the machines to increase immunity to noise on the ground plane of the system and to prevent electrical shock to a user connecting machines at different electrical potentials.
A typical data communication interface is the IEEE 1394-1995 bus system ("IEEE 1394") which is discussed in an article entitled "IEEE Standard for a High Performance Serial Bus" published by the IEEE, which is incorporated by reference herein. The IEEE 1394 is also referred to in the industry as Firewire.TM.. FIG. 1 shows an implementation of a connection to an IEEE 1394 interface using a physical layer device 20 connected to a link layer device 22 by an interface bus 24 device. The physical layer 20 and the link layer device 22 are galvanically isolated by isolation capacitors 26. Resistors 25 and 27 provide proper terminating impedance of the bus lines 24 on either side of the galvanic barrier. It should be understood that the physical layer 20 and link layer devices 22 are in different ground domains.
One problem with the capacitive galvanic isolation barrier is that only time varying signals can pass across the isolation barrier. Thus, constant or D.C. signals asserted on one side of the isolation barrier do not continue to influence signals on the other side of the barrier after they have passed through the isolation barrier. Due to the high input impedance of a device in the receive state on the other side of the barrier (i.e. the device is not driving the line), the line is undriven and can drift to an incorrect logic level.
Techniques, however, exist for ensuring valid logic states on the input of the device. Typically, a form of a voltage limiting circuit, such as a bus holder 30, on each bus line 24 can effectively "square up" the pulses that are transmitted across the isolation capacitor 26. While the bus holder may address some problems, it may also introduce other problems. For example, ground noise may actually cause the bus holder 30 of bus 24 to hold one or more bus lines at an incorrect logic level. The noise on the bus 24 may be mistaken by the bus holder 30 as a change in logic level. The bus holder 30, mistakenly responding to the noise on the ground as a change in logic level, will hold the bus lines at an incorrect logic level.
If the bus holder mistakenly holds the control lines of the bus 24 at an incorrect logic state, the bus may become "locked up" and unable to communicate. It has been observed that a specific cause of the lock up in the case of an IEEE 1394 interface is that the devices can interpret the interface to be active when it is actually idle. For example, a logic high state on a control line between the physical layer device 20 and the link layer device 22 may indicate that the physical layer device 20 is active and has control of the interface. In the IEEE 1394 interface, the busy physical layer device 20 causes the link layer device 22 to relinquish control of the interface. The link layer device 22 will not request control of the interface while the control lines 24 indicate the physical layer device is holding the interface. Thus, a problem may arise if the bus holder 30 mistakenly sets the control lines on the link layer device 22 side of the isolation capacitor 26 after a sequence of state transitions that indicate it is holding the interface when it actually is not holding the interface. While the control lines are at the active logic state, the link layer device 22 will interpret the physical layer device 20 to be active when it is actually idle, and further communication with the physical layer device 20 will not be attempted. The Link device 22 will not attempt further communications until the control lines are returned to the idle state. The system is thus locked up and unable to communicate.
While subsequent data or control activity from the physical layer device may drive a locked line to an idle state and thus reset the interface, the first sequence of data may be lost or corrupted. In addition, narrow duration pulses on the Physical-Link Layer interface bus may be incapable of driving a locked line to an idle state due to the decay time response of the bus 24. FIG. 2 illustrates the inability of narrow pulses to reset the interface. The link layer side 23 of the bus 24 is incorrectly at a logic 1 of high voltage level 33. A narrow pulse 31 on the physical device side 21 of the bus 24 will manifest itself as a transition 41 above the logic 1 level on side 23. A short duration signal bounce 35, however, is not sufficient to cross the threshold 37 for the bus holder 30 to drag the line down to the logic 0 level 56. Instead, the bus line 24 remains at the incorrect logic 1 level 33 and the interface remains locked up. A longer duration pulse will force the incorrectly held side to the correct level because, during the pulse the bus holder will bring the momentary transition above logic level 1 back to the proper logic level 1 voltage. The subsequent high to low transition on the physical layer device side will result in the link layer device side following correctly.
The net result is that the data flow between the physical layer device 20 to the link layer device 22 can become "locked up", i.e., render inoperative communications between the Physical and Link layer devices.